This notebook presents functions that can be used to solve the Reactive Synthesis problem using games. If you are not familiar with how Spot represent games, please read the games notebook first.

In Reactive Synthesis, the goal is to build an electronic circuit that reacts to some input signals by producing some output signals, under some LTL constraints that tie both input and output. Of course the input signals are not controlable, so only job is to decide what output signal to produce.

Reactive synthesis in four steps

A strategy/control circuit can be derived more conveniently from an LTL/PSL specification. The process is decomposed in three steps:

Each of these steps is parametrized by a structure called synthesis_info. This structure stores some additional data needed to pass fine-tuning options or to store statistics.

The ltl_to_game function takes the LTL specification, and the list of controlable atomic propositions (or output signals). It returns a two-player game, where player 0 plays the input variables (and wants to invalidate the acceptance condition), and player 1 plays the output variables (and wants to satisfy the output condition). The conversion from LTL to parity automata can use one of many algorithms, and can be specified in the synthesis_info structure (this works like the --algo= option of ltlsynt).

Solving the game, is done with solve_game() as with any game. There is also a version that takes a synthesis_info as second argument in case the time it takes has to be recorded. Here passing si or not makes no difference.

Once a strategy has been found, it can be extracted as an automaton and simplified using 6 different levels (the default is 2). The output should be interpreted as a mealy automaton, where transition have the form (ins)&(outs) where ins and outs are Boolean formulas representing possible possibles inputs and outputs (they could be more than just conjunctions of atomic proposition). Mealy machines with this type of labels are called "separated" in Spot.

If needed, a separated Mealy machine can be turned into game shape using split_sepearated_mealy(), which is more efficient than split_2step().

Converting the separated mealy machine to AIGER

A separated mealy machine can be converted to a circuit in the AIGER format using mealy_machine_to_aig(). This takes a second argument specifying what type of encoding to use (exactly like ltlsynt's --aiger=... option).

In this case, the circuit is quite simple: o0 should be the negation of previous value of i1. This is done by storing the value of i1 in a latch. And the value if i0 can be ignored.

While we are at it, let us mention that you can render those circuits horizontally as follows:

To encode the circuit in the aig format (ASCII version) use:

Adding more inputs and outputs by force

It can happen that propositions declared as output are ommited in the aig circuit (either because they are not part of the specification, or because they do not appear in the winning strategy). In that case those values can take arbitrary values.

For instance so following constraint mention o1 and i1, but those atomic proposition are actually unconstrained (F(... U x) can be simplified to Fx). Without any indication, the circuit built will ignore those variables:

To force the presence of extra variables in the circuit, they can be passed to mealy_machine_to_aig().

Combining mealy machines

It can happen that the complet specification of the controller can be separated into sub-specifications with DISJOINT output propositions, see Finkbeiner et al. Specification Decomposition for Reactive Synthesis. This results in multiple mealy machines which have to be converted into one single aiger circuit.

This can be done using the function mealy_machines_to_aig(), which takes a vector of separated mealy machines as argument. In order for this to work, all mealy machines need to share the same bdd_dict. This can be ensured by passing a common options strucuture.

Reading an AIGER-file

Note that we do not support the full AIGER syntax. Our restrictions corresponds to the conventions used in the type of AIGER file we output:

An aiger circuit can be transformed into a monitor/mealy machine. This can be used for instance to check that it does not intersect the negation of the specification.

Note that the generation of aiger circuits from mealy machines is flexible and accepts separated mealy machines as well as split mealy machines.