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3.2.26 The src/target/arm Directory

Namespace target::arm, delivered for TC-7. Code generation for ARM. This is not part of the student project, but it is left to satisfy their curiosity. In addition its presence is a sane invitation to respect the constraints of a multi-back-end compiler.

File: cpu.* (src/target/arm)

Description of the ARMV7 CPU.

File: arm-assembly.* (src/target/arm/)

The ARM assembly language (syntax, opcodes and layout); it abstracts the generation of ARM instructions. target::arm::ArmAssembly derives from target::Assembly.

File: arm-layout.* (src/target/arm/)

How ARM fragments are to be displayed. In other words, that’s where the (global) syntax of the target assembly file is selected.

File: arm-codegen.* (src/target/arm/)
File: tree.brg (src/target/arm/)
File: exp.brg (src/target/arm/)
File: binop.brg (src/target/arm/)
File: call.brg (src/target/arm/)
File: temp.brg (src/target/arm/)
File: mem.brg (src/target/arm/)
File: stm.brg (src/target/arm/)
File: move.brg (src/target/arm/)
File: move_load.brg (src/target/arm/)
File: move_store.brg (src/target/arm/)
File: cjump.brg (src/target/arm/)
File: prologue.hh (src/target/arm/)
File: (src/target/arm/)

A translator from LIR to ASSEM using the ARM instruction set defined by target::arm::ArmAssembly. It is implemented as a dynamic programming algorithm generated by MonoBURG from a set of brg files. target::arm::Codegen derives from target::Codegen.

File: target.* (src/target/arm/)

The ARM back-end, based on an ARM CPU and an ARM code generator.

File: runtime.s (src/target/arm/)

The Tiger runtime in ARM assembly language: print etc.