Automatic Variables

Automatic variables are used in much the same way as normal Make variables, except that their value are set automatically by Make according to the suffix rule in which they are used.

In example 5.20, we used a so called automatic variable to refer to the implicit dependency file in a suffix rule. The corollary of this is an automatic variable to refer to the implicit target in a suffix rule. Here is a variation of the suffix rule we added to our Makefile in example 5.20, but using automatic variables to refer to the implicit target and dependency files:

     .c.o:
             $(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@
     

     Example 5.24: Suffix rule to compile C source files
     

$<

In a suffix rule, this variable contains the name of the dependent file that would be needed for the rule to match.

When Make determines that it needs an up to date stackovf.o in order to continue the build, and decides to use this suffix rule to bring it up to date, $< will expand to stackovf.c.

$@

Similarly, this variable contains the name of the target file which matched this suffix rule.

For the same stackovf.o problem above, $@ will expand to stackovf.o.

A small example should crystalise these facts in your mind. Using the following tiny Makefile you can see how this works in practice:

     .c.o:
             @echo '$$< = $<'
             @echo '$$@ = $@'
     

     Example 5.25: Automatic variable setting demonstration
     

You can now create any dummy .c file to match the dependency part of the suffix rule, and ask make to bring a matching target up to date:

     $ touch hello.c
     $ make hello.o
     $< = hello.c
     $@ = hello.o
     

NOTE

GNU Make will actually honour automatic variables in normal dependency rules too, but this is an enhancement beyond what many other implementations of Make allow. If you use this feature in your own project, you can be certain that one of your users will be using a make that doesn't support it, and will be unable to compile your code as a result.