Make Conditionals

GNU Make provides a rich set of conditional directives, with which you can annotate parts of the Makefile to be used conditionally (or ignored). Make conditional directives work in very much the same way as C preprocessor directives (of the GCC chapter (FIXME: xref the preprocessor section of the GCC chapter.)); before the effective contents of a Makefile are parsed, the file is examined and the conditional directives processed to determine what the effective contents of the Makefile are. There are four Make conditional directives, all of which take the following form:

     conditional-directive
             effective if condition is true
             ...
     else
             effective if condition is false
             ...
     endif
     

     Example 5.27: Format of a Make conditional directive
     

The else keyword, and the following false text can be omitted entirely if necessary. There is no need to start the directives in column zero, nor to indent the conditional text blocks any differently than normal. Whatever indentation is given for conditionl text is used verbatim in the effective contents of the Makefile after the directives have been parsed. Should you wish to indent the directives themselves, you must use spaces rather than tabs to avoid fooling Make into thinking the directive is part of a dependency rule command.

The conditional-directive can be one of the following:

ifdef variable-name

The if defined directive tests whether the named Make variable (voir Make Variables) is empty. However, variable-name is not actually expanded: If its value contains anything, even a reference to some undefined Make variable, the effective if condition is true text is passed through to the next stage of the Makefile parser. Converseely, if an else clause is present and variable-name has an empty value, or is not defined at all, the condition fails and the effective if condition is false text is effective.

          OPT        =
          CFLAGS     =
          ALL_CFLAGS = $(OPT) $(CFLAGS)
          all:
          ifdef ALL_CFLAGS
                  @echo true
          else
                  @echo false
          endif
          

Here, the Makefile above will echo true. Although ALL_CFLAGS evaluates to empty, the pre-processing pass merely checks to see if the value of ALL_CFLAGS contains any text - which it does - so the @echo true text is effective.

ifndef variable-name

The if not defined conditional works in the opposite sense to ifdef. By implication, if variable-name has an empty value, or is simply not defined, the effective if condition is true text is effective, otherwise, if an else clause is present, the effective if condition is false text is effective.

          CC =
          ifndef CC
          CC = gcc
          endif
          
          all:
                  @echo $(CC)
          

When parsed by Make, the Makefile above will always echo gcc.

ifeq "argument" "argument"

Unlike the last two conditionals, this if equal directive does expand any variables referenced in either of the two arguments, before they are compared to determine the effective text. If both arguments have the same contents after variable references have been expanded, then the effective if condition is true text is effective.

          ifeq "$(CC)" "gcc"
          CFLAGS = -Wall -pedantic
          endif
          

This example shows how you might change the CFLAGS to give better warnings when compiling with gcc.

ifneq "argument" "argument"

Similarly, there is an if not equal directive, which behaves much the same as ifeq, but obviously with the sense of the test reversed.

          ifneq "$(CC)" "gcc"
          CFLAGS=-g
          else
          CFLAGS=-ggdb3
          endif
          

This Makefile fragment shows how you can set the compiler debugging flags optimally for GCC, without adverse effects when a different compiler is used.

• Make Include Directive: