Shell Commands

You have probably noticed that the command part of the rules shown so far are just executing programs that are also available to users from the command line. In fact, each line of command is evaluated individually. When you write commands that use shell syntax, each line in the command part of the rule is individually executed in its own shell - unless you tie consecutive lines together with backslashes.

     includedir      = /usr/local/include
     include_HEADERS = m4module.h error.h hash.h system.h
     ...
     install-HEADERS: $(include_HEADERS)
             mkdir $(includedir)
             for p in $(include_HEADERS); do \
               cp $$p $(includedir)/$$p; \
             done
     

     Example 5.16: Basic header installation Makefile excerpt
     

In this example, the command consists of only two actual shell commands. The first, mkdir $(includedir), is invoked as a simple one line command; the next command consists of the remaining lines in the rule, because of the \ at the end of each unfinished line.

There is an important distinction to be made here between Make variables, like $(includedir), and shell variables, such as $$p. We have already discussed Make variables in Make Variables. Unfortunately the $ symbol is already used to denote Make variables, and consequently to pass $ through to the shell from the command part of a rule the $ symbol needs to be doubled up: Hence the $$p in this command becomes $p when finally executed by the shell.

Describing how to program in shell is beyond the scope of this book, but you can find terse details in your system manual pages:

     $ man sh
     

See Further Reading for further recommendations. In practice, provided that you use Automake in conjunction with Make, it is quite unusual to need shell programming features in your Makefiles, since all of the complicated commands are generated for you. Automake is dicussed in much more detail later, in Automake.

• Command Prefixes: